Many circuits have one or more buses, each characterized by a node that receives the output signal from two or more devices in the circuit, typically, although not necessarily, tri-state gates. The presence of such buses within a circuit increases the difficulty of testing the circuit by conventional techniques because such techniques often do not maintain the integrity of such buses during testing. Bus integrity is susceptible to several different definitions. The definition appropriate for a specific circuit is often determined by the particular design style used by the designer of the circuit and by the technology and process employed to fabricate the circuit. Most commonly, the integrity of a bus is said to exist, when, following the application of new test stimuli (i.e., new test vectors) to the circuit, the bus is supplied with at most one non-high impedance (i.e., a non-Z) input signal. If two or more non-Z signals are supplied to the same bus under steady-state conditions, then a bus conflict is deemed to exist. Under some circumstances, a bus conflict is deemed to occur if no non-Z input signal is supplied to the bus, as well as if two or more non-Z signals are supplied to the bus simultaneously under steady-state conditions.
Depending on the design of the circuit, and the technology used in its fabrication, bus integrity may be deemed intact as long as all non-Z signals supplied to the bus have the same logic state. Conversely, a bus conflict occurs when two or more of the signals supplied to the bus have a different logic state. Indeed, if the bus is supplied with logic "1" and logic "0" level signals from first and second devices, respectively, during steady-state conditions, then a short is present which could damage the circuit. For the condition when the bus is supplied with different strength signals, bus integrity remains intact as long as all of the highest strength logic signals (non-Z input signals) on the bus have the same logic value following the application of new test stimuli to the circuit. If one or more of the highest strength signals have a logic value different from the other highest strength signals, then a bus conflict occurs.
A circuit, including one containing one or more buses, is usually tested by applying test stimuli to the circuit. There are several known algorithms by which such test stimuli may be generated, so that when the test stimuli are applied, faults in the circuit are detected. Each test stimulus is a vector comprised of specified and unspecified values (the unspecified values being "don't care" values). Heretofore, automatic test stimuli generation algorithms of the prior art have maintained bus integrity by performing bus justification on a global basis within the circuit to justify each bus in advance of the application of each successive test stimulus. Such bus justification was accomplished by determining the values needed at the primary inputs to the circuit to avoid a conflict on each bus and then adding these necessary values to each test vector in advance of its application. As may be appreciated, justifying each bus (i.e., determining the values needed at the primary circuit inputs to avoid a bus conflict) in advance of the application of each successive test stimulus can be time consuming, especially when the number of test vectors to be applied is large.
Thus, there is a need for a technique for maintaining the integrity of each bus in a circuit in connection with testing.